1. Field of the Invention
This invention relates to a shift register for shifting a plurality of bit signals (data) in parallel, and is particularly suitable for a linear feedback shift register used in a circuit for test contained in an LSI.
2. Description of the Related Art
As the integration density of the LSI (large scale integrated circuit) becomes higher and the number of functions thereof becomes larger, the logical test for the input and output of a signal in the LSI becomes more complicated and an amount of data required becomes larger. Therefore, a circuit for test is contained in the recent LSI to reduce an amount of data required for the logical test and test time to minimum.
In the circuit for test, a linear feedback shift register (LFSR) is used for pseudo random data generation or data compression. The LFSR is described in U.S. Pat. No. 4,340,857 "DEVICE FOR TESTING DIGITAL CIRCUITS USING BUILT-IN LOGIC BLOCK OBSERVERS (BILBO'S)" Fasang Jul. 20, 1982 and "DESIGN OF TESTABLE LOGIC CIRCUITS" R. G. BENNETTS ADDISON-WESLEY PUBLISHING COMPANY pp. 62-79, for example. The LFSR is basically constructed by a plurality of latch circuits each formed of a flip-flop circuit, first control gate circuits respectively connected between the plurality of latch circuits and a second control gate circuit for feeding back an output data signal of the last-stage latch circuit to the input node of the first-stage latch circuit. The latch circuits are supplied with a clock signal and the first control gate circuits are respectively supplied with data signals. The data signals are received in synchronism with the clock signals supplied to the respective latch circuits and then sequentially shifted. An output data signal output from each of the output nodes of the latch circuits is supplied to the succeeding-stage latch circuit and derived from each of the latch circuits. An output data signal from the last-stage latch circuit and output data signals from the intermediate-stage latch circuits are supplied to the second control gate circuit for logical operation and then fed back to the input node of the first-stage latch circuit so as to be used as a data signal in the next cycle. The circuit construction of the second control gate circuit and the latch circuit from which it derives data are determined according to the data shift pattern.
In a case where the above LFSR is used for pseudo random data generation, initial values are set into the respective latch circuits by data signals input to the first control gate circuits, the data signals are set to a logical value "0" and then the data in each of the latch circuits is sequentially shifted so that pseudo random data required for the test can be derived from the output node of each of the latch circuits. The output data signal generated as pseudo random data is supplied to the internal portion of the LSI to be tested and the test result is output from the external output terminals of the LSI. On the other hand, in a case where the LFSR is used for data compression, a desired signal to be compressed is supplied as a data signal to the first control gate circuits. The data signal received by each of the latch circuits is sequentially shifted in each of the latch circuits in synchronism with the clock signal and is compressed. As a result, an amount of data necessary for a logical test can be reduced, thus simplifying the test.
It is necessary for the LFSR to have stages of a number corresponding to the number of the input signals necessary for the test when it is used for pseudo random data generation and stages of a number corresponding to the number of the output signals to be observed when it is used for data compression. When the input signal number and output signal number are large in the logical test of the LSI, more precise test result can be generally obtained. Even when a design for testability by dividing the logic circuit into a plurality of logic blocks is used, the input signal number and output signal number will become larger in the divided logic blocks as a whole. Therefore, as the integration density of the LSI becomes larger, the number of stages of the LFSR necessary for the test becomes larger, thereby increasing the occupied area and preventing the LSI from being formed at a high integration density.